![]() ![]() The instantiated component on our test generates outputs as i would in actual use. Stimulus comes from either a test vector file which contains a set of test vectors to test all possible functions of the device, or models in the testbench of external devices that generate signals that are applied to the unit under test. Here's a picture of the structure of a testbench. A testbench can have several functional sections, including the top-level testbench declaration, stimulus and response signal declarations, component declarations, component instantiations, which will put the device under test into the circuit, external stimulation device models, a test process which applies stimulus to the device under test, and a test monitor which reports results. ![]() Most designers spend at least as much time creating testbench code as they do the code for the unit under test. Once you've written your code for a module in Verilog or VHDL, you're not even half done at that point. Its a very powerful tool for auto generating test stimulus and test results, particularly when combined with a simulator like Modelsim in which the Verilog test code will run. The testbench is also sometimes called a test fixture or a test harness. The use of the testbench to auto-generate a stimulus for the unit under test is much more efficient than entering test vectors manually in the simulator, Modelsim in this case. ![]() ![]() In our case, Verilog is going to be used for both the model and the test code. What is a testbench? A testbench is a program written in any language for the purposes of exercising and verifying the functional correctness of the hardware model as coded. You'll learn how to write simple testbenches, and how to use loops to generate stimulus for those testbenches, and how to use assertions to determine and report test results. In this video, you will learn the concept of using a Verilog program called a Testbench to test another Verilog program which will be your code. ![]()
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